Unsolved problems in ferroelectrics for scanning probe microscopy

Scott, J. F. (2005) Unsolved problems in ferroelectrics for scanning probe microscopy. In: Scanning probe microscopy: characterization, nanofabrication and device application of functional materials. NATO Science Series II: Mathematics, Physics and Chemistry, 186 . Kluwer, Dordrecht, pp. 51-73. ISBN 1-4020-3017-7

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Beginning in the 1950s every large US microelectronics company (Bell Labs, IBM, Ford, RCA, etc.) was involved in ferroelectrics research. The main driving force was the idea that the +P polarization state and the –P polarization state of a ferroelectric could be used to encode the “1” and “0” of the Boolean algebra in which modern digital computers operate. At that time, however, ferroelectrics were available only as single crystals or rather thick ceramics. Since a typical coercive field for switching a ferroelectric from +P to –P (or vice versa) is ca. 40 kV/cm, a 1-mm thick device would have an operating voltage of 4000 Volts! Moreover, the devices were expensive. Therefore as silicon DRAM (dynamic random access memories) devices developed rapidly, ferroelectric RAMs were left on the back-burner as objects of mere academic novelty. This changed rapidly through the 1980s as silicon oxide films as thin as 20 nm were fabricated in pinhole-free 6” commercial wafer form. At that point the advantages of ferroelectric memories over Si DRAMs was recognized once again: They are nonvolatile (the memory does not need refreshing, like DRAMs, and does not forget if power is interrupted); they are radiation hard, no single event upset – SEU; and they are lighter in weight than Core magnetic memories, and 1000x faster to erase and rewrite than are EEPROMs – electrically erasable programmable read-only memories). The result has been a ferroelectrics renaissance. Ferroelectric RAMs are now used in smart debit cards at the 16 kbit and 64 kbit level and FRAMs up to 4 Mbit (Figs. 1-3); in SONY Playstation 2 (Fig. 4) and telecommunications. The highest density ferroelectric (FE) chips available are 4 Mbit from Samsung (using chemical solution deposition lead zirconate titanate – PZT – ceramics ca. 40 nm in grain size) and 4 Mbit from Panasonic (using strontium bismuth tantalate – SBT). A fully commercial 8 Mbit ferroelectric RAM is scheduled for production by Infineon (Japan) and Toshiba on 1 September 2003, using sputtered PZT. At present the road map for FRAM technology is well established: by 2008 the linewidth requirements are 0.1 microns; technology node is 70 nm; feature size F is 0.13 microns; 256 Mbit is the size; and complete cycle time is 16 ns. Therefore for this technology, nano-scale is not just a trendy buzz-word; it is a very strict imperative.

Item Type: Book Section
Uncontrolled Keywords: 2006 AREP IA42 IA52 2005 P
Subjects: 03 - Mineral Sciences
Divisions: 03 - Mineral Sciences
Volume: 186
Page Range: pp. 51-73
Identification Number: https://doi.org/10.1007/1-4020-3019-3_3
Depositing User: Sarah Humbert
Date Deposited: 31 Oct 2011 13:00
Last Modified: 23 Jul 2013 09:58
URI: http://eprints.esc.cam.ac.uk/id/eprint/1550

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